Chinese Journal of Computers   Full Text
Title	An Efficient Architecture Method for Improving Energy Efficiency: Parallel Processing
Authors	YI Hui-Zhan LIU Yong-Peng
Address	(Institute of Computer Technology, School of Computer, National University of Defense Technology, Changsha 410073)
Year	2009
Issue	No.12(2475—2481)
Abstract &   Background	Abstract Energy consumption has been paid increasing attention to in the computer domain because of its deep influence on the design of high-performance chips and systems. Many techniques are proposed to improve energy efficiency of computer systems, and in the paper the author focuses on parallel processing on architecture level. Parallel processing improves energy efficiency by using some computing nodes with moderate performance, which maintain high throughput by parallel execution. In this paper, the authors present the fundamental of parallel processing improving energy efficiency, and models the time and energy overhead involved in parallel execution. Based on the models, the author investigates low-voltage parallel systems, parallel systems with dynamic voltage scaling, and multi-core microprocessors, and reveals their potential of improving energy efficiency. Keywords parallel processing; energy efficiency; dynamic voltage scaling; low-voltage design; multi-core processing Background Energy consumption has been paid increasing attention to in the computer domain because of its deep influence on the design of high-performance chips and systems. Many techniques are proposed to improve energy efficiency of computer systems, such as low-power techniques in device design, lower-power techniques in architecture design, low-power techniques in operating systems, and low-power techniques in compilation systems. Although low-power techniques have larger amounts of research work, the power and energy problems have not been completely solved. Since CMOS technology has almost reached to the utmost, the main high-performance processor companies have changed the research way, from high frequency to many cores. Multi-core processors have fully utilized many transistor resources in the silicon chip, and increase the processor performance by task and data parallelism. But considering the energy and time overhead, how parallel processing improves energy efficiency has no a clear scene. In the paper, the author focuses on parallel processing on architecture level. Parallel processing improves energy efficiency by using some computing nodes with moderate performance, which maintain high throughput by parallel execution. In this paper, the authors present the fundamental of parallel processing improving energy efficiency, and models the time and energy overhead involved in parallel execution. Based on the models, the authors investigate low-voltage parallel systems, parallel systems with dynamic voltage scaling, and multi-core microprocessors, and reveals their potential of improving energy efficiency. The project, this paper belongs to, is about power-aware and temperature-aware architecture and compilation research. For developing next-generation high-performance computer, power and thermal problem is one of the most key challenges, and power and thermal management will be one of the primary research directions for high-performance computing. In the project, the authors will investigate software-directed power and thermal management, and the planed works are listed as follows: (1) power and thermal experiment environment and analytical techniques for high-performance computing; (2) OS software directed power and thermal management techniques for high-performance computing; (3) Profile-guided power and thermal management for high-performance computing. In the project, the authors will design experiment environments and submit some excellent papers, and the research achievements will be used to the production tasks for high-performance computing. In this area, the authors have proposed the concepts of architecture energy efficiency and localizing the use of system units, and many works about low-power compilation optimization are published in Chinese journals and English conferences. This paper belongs to power and thermal experiment environment and analytical techniques for high-performance computing.