Chinese Journal of Computers   Full Text
Title	Architecture Supported Synchronization-Based Cache Coherence Protocol for Many-Core Processors
Authors	HUANG He1),2) LIU Lei1),2) SONG Feng-Long1),2) MA Xiao-Yu1),2)
Address	1)(Key Laboratory of Computer System and Architecture, Institute of Computing Technology,Chinese Academy of Sciences, Beijing 100190) 2)(Graduate University of Chinese Academy of Sciences, Beijing 100049)
Year	2009
Issue	No.8(1618—1630)
Abstract &   Background	Abstract The efficient support of cache coherence is extremely important to design and implement many-core processors. This paper proposes a synchronization-based coherence protocol to efficiently support cache coherence for shared memory of many-core processors. The unique feature of the scheme is that it doesn’t use directory at all. Inspired by scope consistency memory model, the protocol maintains coherence at synchronization point. Within critical section, process cores record write sets (which lines have been written in critical sections) with bloom-filter functions. When the core releases the lock, the write set is transferred to a synchronization manager. When another core acquires the same lock, it gets the write set from the synchronization manager and invalidates stale data in its local cache. The scheme is evaluated using programs from SPLASH-2 benchmark. The results show that synchronization-based protocol can achieve similar performance in cost-effective way compared to a directory-based protocol that requires large amount of hardware resources and huge design verification effort. Keywords cache coherence; memory consistency; many-core processors; shared memory system Background The cache coherence protocol is a first-order design consideration in shared memory multicore design. Although distributed directory-based protocols have been proven with fairly scalability, reaching up to hundreds of processors in multiprocessor CCNUMA DSM system, they have many weaknesses preventing it from adapting in many-core architectures. For examples, directory protocols are very difficult to completely debug and verify due to subtle corner cases and tremendous state transitions. There are limited research results related to cache coherence issue for many-core architectures. In this paper, a new hardware cache coherence scheme, architecture supported synchronization-based cache coherence protocol is proposed, which achieves similar performance in cost-effective way compared to a directory-based protocol that requires large amount of hardware resources and huge design verification effort. The project is supported by the National Basic Research Program (973 Program) of China under grant No.2005CB321600 and the National Natural Science Foundation of China under grant No.60736012.