Chinese Journal of Computers   Full Text
Title	SpMT WaveCache: Exploiting Speculative Multithreading for Dataflow Computer
Authors	PEI Song-Wen WU Bai-Feng
Address	(School of Computer Science, Fudan University, Shanghai 200433)
Year	2009
Issue	No.7(1382—1392)
Abstract &   Background	Abstract Speculative Multithreading(SpMT) increases the performance by means of executing multithreads speculatively to exploit thread-level parallelism. The authors expanded the transactional memory system of WaveCache by adding extra hardware components, such as Thread Synchronization Unit(TSU), Thread Context Table(TCT) and Thread Memory History(TMH), to improve the performance of SpMT WaveCache which is built on WaveScalar instruction set architecture(ISA). Furthermore, a novel two-levels commit method is proposed to support submitting thread-level transactions. Finally, the SpMT WaveCache is evaluated with 6 real benchmarks selected from SPEC, Mediabench and Mibench benchmarks. According to the experimental results, the SpMT WaveCache outperforms superscalar architecture ranging from 2X to 3X, and it also performs greater gain over original WaveCache and Transactional WaveCache. Therefore, the SpMT WaveCache is a good way to exploit thread-level parallelism of dynamic dataflow computer. Keywords dynamic dataflow computer; speculative multithreading (SpMT); transactional memory; WaveScalar Background This paper aims at examining computer architecture, specifies the dynamic dataflow computer architecture. Recent years, the researches on dataflow computer architecture are popular and many prototyping systems or architectures are growing with respective properties and advantages. As for WaveScalar architecture, one of the most advantages is that programs coded in the compelling programming language such as C can be executed on it without further revised. It was firstly proposed by the computer architecture research team within Washington University, but it lacks of exploiting speculative multithreads and transactional operations. Last year, Leandro Marzulo’s team that is one of our cooperators, proposed Transactional WaveCache by adding transaction memory system. The authors exploited speculative multithreading on the WaveCache simulator (SpMT Wavecache) by propounding Thread Synchronization Unit, Thread Context Table and Thread Memory History table, and extended the transactional memory system. According to the experimental results based on 6 real benchmarks selected from SPEC, Mediabench and Mibench, the SpMT Wavecache outperforms superscalar architecture ranging from 2x to 3x. It’s our first step to exploit high performance of WaveScalar dataflow computer architecture. The authors will propose and elevate a novel Cache Hierarchy for WaveCache in the following months. The research activities were accomplished at the cooperative Lab of AMD Advanced Processor within School of Computer Science, and the research was sponsored by Shanghai Leading Academic Discipline Project (B114) and AMD’s University Cooperation Program. The authors appreciate that many helpful suggestions and discussions from Leandro Marzulo with Universidade Federal do Rio de Janeiro, Andrew Putnam with University of Washington, USA and Elias Mizan with University of Texas at Austin, USA. In the past years, the second author engaged in theoretical research on dynamic dataflow computer and embedded system design (Phoneix and Phoniex II) based on the principle of Dynamic Dataflow (DDF), and published more than 10 impressive papers on computer related scientific journals and conference.