¡¡Chinese Journal of Computers   Full Text
  TitleAnalysis of Coupling Capacitance among Interconnections Based on Defect¡¯s Uniform Distribution
  AuthorsDUAN Xu-Chao1),2) ZHAO Tian-Xu1)
  Address1)(Institute of Computation and Information, Baoji College of Arts and Sciences, Baoji, Shaanxi 721007) 2)(Physics and Information Technology Department, Baoji College of Arts and Sciences, Baoji, Shaanxi 721007)
  Year2009
  IssueNo.6(1147¡ª1151)
  Abstract &
  Background 		Abstract The parasitical effect is one of the key factors that restrict the VLSI development forward high speed and high density. In this paper, the parasitical capacitance affected by the defects in the IC manufacturing among interconnections is analyzed and the model of the parasitical capacitance is given. The simulation results show that the extra electric defect makes the parasitical capacitance increase under given a space between interconnections in this paper. Keywords defect; delay; interconnection; parasitical capacitance; coupling capacitance Background This research belongs to the project of ¡°Study on the Related Problems to Yield and Reliability of the Deep Submicron meter Devices¡± supported by the Shaanxi Province Natural Science Foundation¡¡(No.SJ08-ZT13). There are three parameter that significantly affect yield and reliability of ICs: (1)¡¡a design-related parameter, such as chip area and gate oxide thickness; (2)¡¡a process-related parameter, such as defect distribution and density; (3)¡¡an operation-related parameter, such as temperature and voltage. In general, reliability depends upon all three parameters, whereas yield is affected by design and process-related parameters. Therefore, defect is one of important factors affecting IC yield and reliability. The authors have researched on the effect of defect to IC yield and reliability. They propose the critical area model of yield of tolerant circuit and the lifetime estimation model of integrated circuit with defective interconnect. These researches are the main problems of the design for manufacturability of integrated circuits.