Chinese Journal of Computers   Full Text
Title	Pipelined Template for Mapping Multiple Loop Nests on FPGA with Restricted Resources
Authors	DONG Ya-Zhuo1) DOU Yong2) SONG Jian3) Liu Ming-Zheng4)
Address	1)(Unit 91655, People’s Liberation Army, Beijing 100036) 2)(School of Computer, National University of Defense Technology, Changsha 410073) 3)(Unit 61785, People’s Liberation Army, Beijing 100075) 4)(Application Laboratory, Logistic Science and Technology Research Institute, Beijing 100071)
Year	2009
Issue	No.1(152—160)
Abstract &   Background	Abstract FPGA provides a convenient and flexible solution to speed up loop-intensive algorithms. However, these loop nests in a large scale application have to be mapped onto the target FPGA orderly because of the limited resources on-chip. FPGA reconfiguration which needs a long time is inevitable when switching between the loop nests. This paper presents a pipelined template and instruction schedule method corresponding to execute all the loop nests in sequence without FPGA reconfiguration. Experiments show that the pipelined template can achieve a comparative execution cycles for a loop comparing with the special hardware and without the need of FPGA reconfiguration. Keywords loop; FPGA; pipelined template; instruction schedule Background This paper is mainly supported by the National Natural Science Foundation of China (60633050). This project aims to deal with the urgent science computation requirements of our country, research the pivotal technologies of high-efficiency parallel computer architecture. Based on the analysis of some typical applications, a series of studies are carried through, including memory architecture, hardware acceleration and high level synthesis etc. More than 20 papers of the team was published in international conference and journals including FPGA2005, ASP-DAC 2007 and ASAP2007 etc. The authors’ work was used in high level synthesis. High Level Synthesis (HLS) tools provide a bridge between the algorithm written in a high level language (Matlab, C, C++, etc.) and a lower level Hardware Description Language (HDL). They concentrates on one class of applications called window operations. This kind of applications is widely used in signal, image and video processing and requires much computation and data manipulation. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these algorithms. This paper presents a pipelined template and instruction schedule method corresponding to execute all the loop nests in sequence without FPGA reconfiguration. Experiments show that the pipelined template can achieve a comparative execution cycles for a loop comparing with the special hardware and without the need of FPGA reconfiguration. Thus the pipelined template is better.