| ¡¡ | Chinese Journal of Computers Full Text |
| Title | Research and VLSI Implementation of a Dynamic Virtual Channel Structure with Congestion Awareness Scheme. |
| Authors | LAI Ming-Che WANG Zhi-Ying GUO Jian-Jun DAI Kui |
| Address | (School of Computer, National University of Defense Technology, Changsha 410073) |
| Year | 2008 |
| Issue | No.11(2026¡ª2037) |
| Abstract & Background | Abstract The virtual channel flow control approach provides an efficient way for the high throughput of on-chip routers. However, allocating the virtual channels statically results in a waste of area and energy consumption. Through the analysis towards shortcomings of statically-allocated virtual channels, a novel dynamic virtual channel structure with congestion awareness scheme is proposed. The buffer resources are organized by linked lists and their structures regulated according to the traffic conditions. In low traffic, it produces few deep channels to reduce the packet latency. In high traffic, it dispenses many VCs and avoids congestion situations to improve the throughput. The VLSI implementation of DVC router is completed under 90nm CMOS process. The experiment results show that the DVC router which suits for the various inject ratios and traffic patterns can provide throughput increase and latency decrease, with the obvious savings of silicon area and power consumption when compared to traditional routers. Keywords network-on-chip; virtual channel; delay; throughput; VLSI implementation |