| ¡¡ | Chinese Journal of Computers Full Text |
| Title | Multi-Core Embedded Processor Based on FPGA and Parallelization of SUSAN Algorithm |
| Authors | WANG Jie ZHANG Shu-Yan LIU Tao JI Zhen-Zhou HU Ming-Zeng |
| Address | (Department of Computer Science and Technology£¬ Harbin Institute of Technology£¬ Harbin 150001) |
| Year | 2008 |
| Issue | No.11(1995¡ª2004) |
| Abstract & Background | Abstract Structure of 4-core embedded parallel processor is presented and FPGA validation platform that is called FPEP is built. To evaluate performance of multi-core processor platform, three feasible parallel algorithms with OpenMP on SUSAN that is a classic image processing algorithm: direct parallel SUSAN, image block processing and parallel processing of multiple images are proposed, and performance testing of these three parallel algorithms execute on Intel 4-core platform and FPGA validation platform of FPEP. Experimental results demonstrate that speedup ratio of three parallel algorithms on both 4-Core platforms is approximate 3.0£¬and speedup ratio of parallel processing of multiple images on FPGA validation platform of FPEP is approximate 4.0. Keywords SUSAN; FPGA; OpenMP; multi-core processor; image processing |