| ¡¡ | Chinese Journal of Computers Full Text |
| Title | Architecture of PKUnity-SK SoC for UMPC |
| Authors | CHENG Xu LU Jun-Lin YI Jiang-Fang LIU Shu |
| Address | (Micro Processor Research and Development Center, Peking University, Beijing 100871) |
| Year | 2008 |
| Issue | No.11(1877¡ª1887) |
| Abstract & Background | Abstract How to meet the requirement of 3C fusion better, is the very key point of popularization of Ultra-Mobile Personal Computer (UMPC). PKUnity-SK SoC integrates the CPU, North/South Bridge chipsets, display controller and other I/O devices, which are distributed on the main board in traditional computer, into one single chip. Beyond the efficient processing of multimedia, PKUnity-SK SoC adopts 2D/3D extension instruction, HW/SW cooperated video decoding accelerator as well as hardware supported video encoding/decoding to reduce the demand for CPU performance. The hierarchical storage system in a single chip simplifies the data transfer path and increases the data transfer rate to improve the system performance. Furthermore, many popular I/O controllers are implemented on the SoC to satisfy I/O usage in personal computer. The design of PKUnity-SK SoC achieves the goal of high-integration, high performance and low power, providing a UMPC solution in low cost, low power, easy usage and easy maintenance for education, electronic government, and personal information processing. Keywords system-on-chip; ultra-mobile personal computer; multimedia acceleration; hierarchical storage |