Chinese Journal of Computers   Full Text
Title	A Test Data Compression Scheme Based on Mixed Fixed and Variable Length Coding
Authors	ZHAN Wen-Fa1),2) LIANG Hua-Guo1) SHI Feng1) HUANG Zheng-Feng1)
Address	1)(School of Computer and Information, Hefei University of Technology, Hefei 230009) 2)(Department of Educational Technology, Anqing Normal College, Anqing, Anhui 246011)
Year	2008
Issue	No.10(1826—1834)
Abstract &   Background	Abstract A test data compression scheme based on fixed and variable length coding (FAVLC) is presented, by using which the test data can be compressed efficiently. In the scheme code words is divided into fixed length head, which eases the control of decompression, and variable length tail, which adds the feasibility of encoding. In order to obtain further compression effect, the highest bit of the tail is reduced from the code words. In addition, a special shift counter is also used, which further ease the control circuit. Experimental results show that the proposed scheme obviously outperforms the traditional coding methods in the compression ratio and the implementation of decompression, such as Golomb, FDR, VIHC, v9C coding. Keywords test data compression; coding; built-in self-test; fixed length coding; variable length coding Background As the size and the complexity of systems on a chip continue to grow, test data volume has increased dramatically. In order to apply the large volume of test data to a chip under test, the automatic test equipment(ATE) requires large memory storage and high bandwidth, so resulting in test cost increases. To reduce test cost, test data compression schemes were proposed. One of the promising category of test data compression schemes uses different coding techniques for compression. Coding, which compresses the data according to the length of runs in the test data, is one of the effective test data compression methods. It involves partitioning the original data into symbols, and then replacing each symbol with a code word to form the compressed data. According to the volume of the symbol in original data and code word in compressed data, the coding schemes can be divided into four types: fixed-to-fixed-length, fixed-to-variable-length, variable-to-fixed-length, variable-to-variable-length. In this paper, a new test data compression scheme based on fixed and variable length coding (FAVLC) is presented, whose codewords are divided into fixed length heads, which eases the control of decompression, and variable length tails, which adds the feasibility of encoding. Furthermore, the highest bit of the tail is reduced from the code words. In addition, a special shift counter is also used, which further ease the control circuit. Compared with the previous schemes, the proposed scheme can increase the encoding efficiency with less hardware overhead. This work is supported in part by the National Natural Science Foundation of China (No.90407008, No.60633060) and Natural Science Foundation of Education Agency of Anhui Province of China under grant No.KJ2008B031. The research topic is to develops test data compression techniques so as to reduce test cost. In the research group, lots of researches have been achieved to solve the problems and many efficient test data compression schemes have been presented. For example: (1) Efficient test data compression and decompression based on alternation and run length codes. (2) Test data compression scheme based on variable-to-fixed-plus-variable-length coding. (3) A deterministic BIST scheme based on reseeding of folding counters. (4) Block Marking and Updating Coding in Test Data Compression for SoC.