Chinese Journal of Computers   Full Text
Title	Regulating SMT Resource Allocation via Thread-Sensitive Register Renaming
Authors	YANG Hua1) CUI Gang2) LIU Hong-Wei2) YANG Xiao-Zong2)
Address	1)(School of Computer, Shenyang Institute of Aeronautical Engineering, Shenyang 110136) 2) (School of Computer Science and Technology, Harbin Institute of Technology, Harbin 150001)
Year	2008
Issue	No.5(845—857)
Abstract &   Background	Abstract SMT processors generally regulate the resource allocation indirectly by controlling the Instruction-Fetch(I-Fetch) process, which may lead to resource misuse and even starvation, incurring resource underutilization and performance depression. Various improving techniques have been proposed; however their effects are discounted due to either being too expensive to implement, or failing in eliminating the imbalance of resource allocation. This paper proposes a novel scheme, Thread-Sensitive Register Renaming(TSRR), which serves as a resource gating, remarkably eliminating the imbalance of resource allocation and improving the overall performance. TSRR features that: (1) it tracks the performance variations and dynamically tunes the resource amount available to each thread, realizing allocation-on-demand, (2) it is cost-effective because it tunes up all resources just by regulating the allocation of the rename-register-file (RRF), and (3) concerning both effectiveness and fairness, TSRR prevents both resource misuse and starvation, whereas fully exploits the performance potential of each thread. Meanwhile, TSRR can lessen the RRF size demands and I-Fetch hardware complexities. Keywords SMT； resource allocation； register renaming； processor； high-performance Background SMT plays a staple role in the forthcoming chip multithreading era, and the way how resources are allocated in the SMT processors consequently has a great impact on the overall performance. Having made an extensive survey and in-depth analysis, the authors find the imbalance of resource allocation is the fatal reason why resource underutilization and performance depression present themselves in various improving techniques. Accordingly, the authors propose a cost-effective scheme named TSRR，reaching allocation-on-demand and concerning both effectiveness and fairness. This work is supported by the 10th 5-Year Pre-Research Project under grant No.41316.1.2, the National Natural Science Foundation of China under grant No.60503015, and the Ph.D. Supporting Foundation from the Ministry of Education of China under grant No.20020213017. An important objective of the projects is to research and develop high-performance and reliable computer systems, which ultimately rely on high-performance and reliable processor architectures.