Chinese Journal of Computers   Full Text
Title	Reversible Logic Synthesis with Positive/Negative Control Model
Authors	GUAN Zhi-Jin1),2) QIN Xiao-Lin1) SHI Quan2) ZHENG Ji-Ping3)
Address	1)(College of Information Science and Technology, Nanjing University of Aeronautics and Astronautics, Nanjing 210016) 2)(College of Computer Science and Technology, Nantong University, Nantong, Jiangsu 226019) 3)(Department of Computer Science and Technology, Tsinghua University, Beijing 100084)
Year	2008
Issue	No.5(835—844)
Abstract &   Background	Abstract Based on traditional Toffoli gate, a new reversible network cascade model PNCRC is proposed. The model consists of five line-styles, and it is able to control output of target bits with positive/negative way effectively. A reversible synthesis algorithm corresponding to the proposed model is also designed in this paper. Compared to the previously reported results, some experiments on NCMC Benchmark functions (less than or equal 16 variables) show that PNCRC decrease the number of garbage output and number of reversible gates as a whole. Keywords reversible logic; quantum gate; garbage; positive/negative control; reversible network Background This work is supported by the National Natural Science Foundation of China under grant No.60673127, the National High Technology Research and Development Program (863 Program) of China under grant No.2007AA01Z404, and Natural Science Foundation for colleges and universities of Jiangsu province of China under grant No.05KJB520107. Reversible logic synthesis is considered as a rapidly developing research area. Interest in reversible logic is sparked by its necessity in quantum technologies. Reversible implementations are also found in cryptography, Information security, nanotechnology, and so on. The amount of reversible logic gate and amount of garbage are a very important criterion for a good synthesis procedure, since in most technologies the addition of only one bit of garbage is expensive or even impossible to implement. Based on this information, a crucial way to help reversible logic to evolve and become usable is to design a synthesis method which uses the theoretically minimal number of reversible gate and number of garbage bits. In this paper, a reversible network cascade model is provided. This model can be controlled with positive/negative, and the algorithm of reversible synthesis is proposed for the model. Using the approach, the authors create a program and run it to synthesis the NCMC Benchmark functions with less than twelve variables. The experimental results show a proper improvement for the number of garbage outputs and number of gates, and the method can minimize the number of NOTs in reversible network.