Chinese Journal of Computers   Full Text
Title	Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor using WDDL and Wave-Pipelining
Authors	TONG Yuan-Man WANG Zhi-Ying DAI Kui LU Hong-Yi SHI Wei
Address	(School of Computer, National University of Defense Technology, Changsha 410073)
Year	2008
Issue	No.5(827—834)
Abstract &   Background	Abstract Novel design method and design flow of block cipher is presented based on the WDDL (Wave Dynamic Differential Logic) and Wave-Pipelining techniques. This design flow utilized the current commercially available EDA tools to a large degree. The WDDL and wave-pipelining based coprocessor not only resists power analysis, but also achieves high performance and low power consumption in nature. According to the design flow, this paper implements a DES coprocessor. The simulation results show that the novel design method achieves high performance, low power consumption and power analysis resistant ability at the cost of chip area. Keywords power analysis attack; WDDL; wave-pipelining; block cipher; coprocessor; high performance; design flow Background Power analysis attack is firstly proposed by P.Kocher in 1999. It is a very powerful attack to break the stored secret key in secure chip such as smart card. And it can be used to break almost all kinds of implementations of cryptographic algorithms without appropriate countermeasures. The countermeasures to prevent power analysis attack are divided into two groups. The one is to randomize the power consumption, and the other one is to make the power consumption constant, i.e. independent of the secret key. To achieve constant power consumption, several novel logic styles are proposed. These logic styles include SABL (sense amplifier based logic), WDDL (wave dynamic and differential logic), and MDPL (masked dual-rail and pre-charge logic) etc. And these novel logic styles have been used to implement different block cipher coprocessors. However, the hardware complexity, power consumption are greatly increased, and the performance is decreased. The authors have studied the SABL and implemented a standard cell library of SABL, and also proposed a semi-custom design flow of the hybrid implementation based on the static standard cell and SABL. The research of this paper belongs to the project (No. 60706026) funded by the Natural Science Foundation of China (NSFC). The main goal of this project is to research semi-custom design flow of power analysis resistant cryptographic devices, to research efficient countermeasures, design and implementation of secure SoCs (system on chip). In this paper, the WDDL and wave-pipelining are combined to implement power analysis resistant and high performance block cipher coprocessors. And the methodology to implement cryptographic coprocessors is presented and the experiment result of a practical DES coprocessor is shown.