Chinese Journal of Computers   Full Text
Title	Using Instruction Fetch Policy to Control Performance of a Thread in SMT Processors
Authors	SUN Cai-Xia ZHANG Min-Xuan
Address	(School of Computer Science, National University of Defense Technology, Changsha 410073)
Year	2008
Issue	No.2(309—317)
Abstract &   Background	Abstract Currently, fetch policies in Simultaneous Multithreading (SMT) processors almost focus on overall performance optimization, and provide no control over how individual threads are executed. A novel fetch policy called CPIT (Controlling Performance of Individual Thread) is proposed to control the execution of a particular thread in SMT processors. Results show that for more than 94% of all cases measured, CPIT can control the execution and consequently achieve the desired performance for a given thread. For the failing cases, the average variance is within 1.25%. Furthermore, CPIT does not sacrifice overall performance of SMT processors severely. Compared to fetch policies orienting towards performance maximization such as ICOUNT, the average degradation of overall performance is not more than 3% and the degradation of threads other than the given thread in performance is only 1.75%. keywords Simultaneous multithreading; instruction fetch policy; performance; resource allocation; desired performance background This paper focuses on fetch policies in Simultaneous Multithreading (SMT) processors and studies how to control the performance of a particular thread in SMT processors by fetch policies. Currently, fetch policies in SMT processors almost aim at how to optimize overall performance, and provide no control over how individual threads are executed. In this paper, a novel fetch policy called CPIT (Controlling Performance of Individual Thread) is proposed to implicitly control the execution of a particular thread in SMT processors and how to implement CPIT is detailed also in this paper. According to the analysis and experiments, CPIT is proved to be practical and effective. For more than 94% of all cases measured, CPIT can control the execution and consequently achieve the desired performance for a given thread. For the failing cases, the average variance is within 1.25%. Furthermore, CPIT does not sacrifice overall performance of SMT processors severely. Compared to fetch policies orienting towards performance maximization such as ICOUNT, the average degradation of overall performance is not more than 3% and the degradation of threads other than the given thread in performance is only 1.75%. This work is supported by the National Natural Science Foundation of China under grant No.60376018 and the National High Technology Research and Development Program (863 Program) of China under grant No.2005AA11002. Both projects study the design of high-performance general processors and hope to make a contribution to processors made in our country. Their work mainly focuses on the microarchitecture, especially on multithreading and single chip multiprocessors. The research group has achieved much. Over one hundred papers were published and seven patents were granted. Over ten students had MS and four students had PhD with the support of these two projects.