Chinese Journal of Computers   Full Text
Title	Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture
Authors	ZHOU Zhi-Xiong HE Hu YANG Xu ZHANG Yan-Jun SUN Yi-He
Address	(Institute of Microelectronics, Tsinghua University, Beijing 100084)
Year	2008
Issue	No.1(127—132)
Abstract &   Background	Abstract Generally VLIW(Very Long Instruction Word) processors are implemented as bus-connectivity clustered architecture, in which the function units in a cluster only access the corresponding local registers and different clusters are connected by buses. This architecture can avoid aggressive growing of delay, area and power in full-connectivity VLIW processors when function units increase. However, performance degradation is induced by its copy operations and latency of communications between clusters. This paper presents a new clustered architecture, in which a register file is used to connect all the clusters so as to turn copy and latency away. This paper also gives instruction scheduling algorithm to improve the performance. The experimental results indicate that this new architecture under the help of this scheduling algorithm shows only 13% performance degradation and little code size increase in average compared with those of fully connectivity VLIW architecture, which prevails that of bus-connectivity clustered VLIW architecture. keywords VLIW; instruction scheduling; register file background This work is supported by the National Natural Science Foundation under grant No.60236020. VLIW architecture is adopted in most high performance media processors, such as TI C6000 series. Generally they are implemented as clustered VLIW so as to achieve less area and lower power. The authors present a new clustered VLIW architecture which can give comparative area and power but higher performance and shorter code size. Up to now the authors have finished designing of a DSP based on this new architecture. Performance of VLIW processors depends on the compiler, so it is necessary to make research on compiler technology aimed to this new architecture. This paper gives overview and analysis of this new architecture, and then presents instruction scheduling algorithm to improve the performance.