| ¡¡ | Chinese Journal of Computers Full Text |
| Title | A New VLSI Architecture for Fractional Motion Estimation of H.264/AVC |
| Authors | ZHENG Zhao-Qing1) SANG Hong-Shi1) LAI Xiao-Ling1) SHEN Xu-Bang1),2) |
| Address | 1)(Institute for Pattern Recognition and Artificial Intelligence, Huazhong University of Science and Technology, Wuhan 430074) 2)(Xi¡äan Microelectronics Technology Institute, Xi¡äan 710054) |
| Year | 2007 |
| Issue | No.12(2101¡ª2108) |
| Abstract & Background | Abstract This paper presents a new VLSI architecture for fractional motion estimation of H.264/AVC. The first time changed loop order of fractional motion estimation algorithm, from 1/2-pixel and 1/4-pixel sequential search to parallel search. This improvement results in designing a high parallel VLSI architecture. And this architecture reduces the requirements for memory access because it doesn¡®t need to input and output 1/2 interpolation data. It takes 1334 cycles to find 41 motion vectors of one macro-block with 1/4-pixel precision. This architecture has been designed and synthesized in HJIC 0.18¦Ìm technology. When operating at 147MHz, it consists of 276k gates and can meet SDTV(1280¡Á720)@30Hz video coding requirements. Compared with other architectures, it reduces requirements for memory access and improves data throughput. keywords H.264; VLSI architecture; block matching; motion estimation; video coding background The H.264/AVC video compression standard, jointly developed by ITU-T and ISO/IEC, provides at least 2x compression improvement and substantial perceptual quality enhancement over all previous standards but significantly increases the computation complexity. In particular, the motion estimation results to be the most intensive task in the whole encoding process. Some new features of the standard that enable enhanced coding efficiency by accurately predicting the values of the content of a picture to be encoded are variable block-size, quarter-sample-accuracy and multiple reference picture for motion estimation and compensation. Experimental results have shown that motion estimation can consume 60% for 1 reference frame to 80% for 5 reference frames of the total encoding time of H.264 codec. For this reason, in order to get real time performance from a H.264 encoder, parallel processing must be exploited in the architecture. 41 fractional motion vectors (MVs) in one macro-block (MB) are derived from one integer MV, in fact, 41 integer MVs may point to different positions. Because this method restricts search range, the performance of rate-distortion will decrease, especially for large motion video. In 41 half pixels MVs are derived from 41 integer pixels MVs, then 41 quarter pixels MVs are derived from 41 half pixels MVs. This hierarchical refining increases requirement of memory access bandwidth. This paper proposes a new VLSI architecture for fractional motion estimation (FME) of H.264/AVC. This architecture implements all fractional pixels interpolation and uses 49 4-parallel PEs. It can meet SDTV(1280¡Á720)@30Hz video coding motion estimation requirements. This project supported by the Hubei Natural Science Foundation of China(No. 2006ABA087). The authors proposed integer motion estimation VLSI architecture for H.264 before. These achievements help to design high performance H.264 video codec. |