Chinese Journal of Computers   Full Text
Title	Dynamic Implicit Predication Based on Lite Trace Cache
Authors	TANG Yu-Xing DENG Kun DOU Yong ZHOU Xing-Ming
Address	(National Key Laboratory of Parallel and Distributed Processing, School of Computer, National University of Defense Technology, Changsha 410073)
Year	2007
Issue	No.11(1972—1981)
Abstract &   Background	Abstract To exploit instruction level parallelism, modern microprocessor usually converts control dependences into data dependences. If-conversion and predicated execution are widely adopted to eliminate branch misprediction penalty. In this paper, a trace-based predicate mechanism named DIP(Dynamic Implicit Predication) is discussed. Previous predication execution depends on compiler to generate explicit predicated instructions. The candidates of if-conversion will be identified during dynamic execution. Classical trace cache has been modified to store DIP traces, which include instructions both from fall-through and target block behind the conditional branch. Hardware will add predication to DIP trace automatically. With the help of DIP, legacy applications can benefit from predication mechanism without recompiling source code. Simulation of DIP under various hardware configurations is presented in the paper. Results have shown promising performance improvement. For SPEC INT2000 benchmark, average IPC(Instruction Per Cycle) improvement achieves 10.3%, and average speedup of execution time is 7.59%. keywords ILP; predication; dynamic implicit predication; trace cache; pipelining background This paper’s work belongs to the research of microarchitecture and dynamic optimization. Recently, several international research groups present their own framework and new optimization algorithm. And this research direction, combined with binary translation and virtualization, is just take-off. Researches use different new predictor hardware to solve the branch problem. But always there are some branches which are hard to predict. This paper uses the predication mechanism to solve these hard-to-predict branches. DIP(Dynamic Implicit Predication) combines the simple hardware extension and trace optimization, which can be treat as a novel dynamic optimization method. This paper’s work is a part of the team works of ARCH group in parallel and distributed processing laboratory(PDL of School of Computer, National University of Defense Technology). After 10 more years research in architecture of high performance computer and microprocessor, ARCH group had many breakthroughs in MT, CMP, Trace scheduling, Dynamic Translation and Optimization. Now the group focuses on design microprocessor based on dynamic translation and optimization. DIP has been used in the architecture design of the proposed processor. And it solves the performance problem of hard-to-predict branch, but still keep the original ISA unchanged.