Chinese Journal of Computers   Full Text
Title	FT51：A Soft Error Tolerant High Reliable Micro Controller
Authors	GONG Rui CHEN Wei LIU Fang DAI Kui WANG Zhi-Ying
Address	(School of Computer, National University of Defense Technology, Changsha 410073)
Year	2007
Issue	No.10(1662—1673)
Abstract &   Background	Abstract This paper proposes a soft error tolerant high reliable micro controller, FT51. Temporal spatial triple modular redundancy based on asynchronous circuit technique is designed to tolerate SEU (Single Event Upset) in sequential logic and SET (Single Event Transient) in combinational logic. On-chip memory is protected by Hamming code. Control flow checking and recovering by compiler signature and hardware checking is designed to reduce performance overhead and binary code size overhead in traditional software implemented control flow checking. A reliability evaluation method is also proposed in this paper. FT51 is implemented in HJTC 0.25μm process, with 80.6% area overhead and 19%~133% performance overhead. The results of simulation and theoretical verification indicate that FT51 can mask or detect 99.73% faults under typical condition. keywords micro controller; soft error; single event upset; single event transient; temporal spatial triple modular redundancy; control flow checking background Microprocessors now are widely used in space environment, which consists of various high-energy particles. The particle-induced soft errors threaten reliability of integrated circuits and systems in space. Moreover, the number of nodes in a chip keeps increasing with shrinking feature size, and the charge stored in a node keeps decreasing with lower supply voltage. As a result, low-energy particles that once were considered negligible now are able to affect the operation of microprocessors. An ideal soft error tolerant microprocessor for space applications should fulfill the following requirements: (I) tolerating frequent faults, including Single Event Upset (SEU) and Single Event Transient (SET); (II) implementing with reasonable area and performance overheads; (III) supporting fast recovery from errors; (IV) implementing in commercial design flow and manufacture process. Since Intel 8051 series micro controllers are widely used in many space applications, the authors designed and implemented a soft error tolerant 8051, FT51. The temporal spatial triple modular redundancy based on asynchronous circuit technique is proposed to protect registers against both SEU and SET, with reasonable chip area overhead comparing to conventional methods. The control flow checking and recovering by compiler signatures and hardware checking is also designed to implement fast recovery from control flow errors. All hardening techniques in the authors’ design can be implemented in commercial design flow. A theoretical evaluation approach is presented, in which the chip area is used as an important parameter to evaluate the microprocessor’s reliability after hardening. This work is supported by the National Natural Science Foundation of China under grant No. 90407022. The NSF project aims to solve the design methodology of asynchronous circuit and explore the fault tolerant ability of asynchronous circuit. The research work of this paper belongs to the fault tolerant ability of asynchronous circuit. As is presented, the register is protected by temporal spatial triple modular redundancy based on asynchronous circuit. In this field, the authors have published two papers. One is "Modified triple modular redundancy structure based on asynchronous circuit technique" in DFT’06, the other is "A new approach to single event effect tolerance based on asynchronous circuit technique" in Journal of Electronic Testing: Theory and Applications by Springer (accepted).