¡¡Chinese Journal of Computers   Full Text
  TitleLow Power State Assignment of FSMs Targeting Multi-Level Logic Implementations
  AuthorsYE Xi-En XIA Yin-Shui TAO Wei-Jiong
  Address(Institute of CAS, Ningbo University, Ningbo£¬ Zhejiang 315211)
  Year2007
  IssueNo.9(1567¡ª1572)
  Abstract &
  Background 		Abstract State assignment has been shown to be an effective method for low power FSM design. This paper presents a new cost function targeting multi-level combinatorial logic implementation. Using whole annealing genetic algorithm, low power state codes are obtained to reduce the switching activities and the area of the combinatorial logic, which reduce the average power of the FSM. The proposed algorithm is tested on 25 benchmarks. Compared with published area and power optimization algorithms, the proposed algorithm can save much more power dissipation and has advantage on area improvement.

keywords FSM;low power;state assignment;whole annealing genetic algorithm; multi-level logic

background This work is part of the project supported by the National Natural Science Foundation of China under grant No.60676017. With the rapid increase of chip size, power dissipation has been a critical issue in VLSI design. Low power design technique is a critical need for today¡¯s VLSI industry. Since most of digital systems are sequential systems and sequential system is modeled by FSM, it is great important to develop low power FSM design techniques. In low power FSM design, state assignment is one of the important methods. Minimizing the transitions between FSM states can reduce power dissipation and good state assignment can reduce significantly state transitions. However, area tradeoff may incur. Therefore, a good optimizing technique is required based on state assignment.
The research group has worked on this project for five years and published 11 academic papers in IEE Proceedings of Computer Digital Techniques, Journal of Computer Science and Technology, Journal of Computer Aided-Design and Graphics, and so on. The authors have proposed low power state assignment techniques targeting two level FSM design, partitioned based low power FSM design techniques, etc. This work aims to solve the problem targeting power and area optimization for multilevel FSMs.