Chinese Journal of Computers   Full Text
Title	Power Consumption and Process Variations: Two Challenges to Design of Next-generation Ics
Authors	LUO Zu-Ying
Address	(Department of Electronic Engineering, Beijing Normal University, Beijing 100875) (Key Laboratory of Computer System and Architecture, Chinese Academy of Sciences， Beijing 100080)
Year	2007
Issue	No.7(1054—1063)
Abstract &   Background	Abstract Famous IC vendors including Intel, AMD, IBM have scaled their IC technologies into 65nm. High-end IC design aiming at high performance has faced many challenges from cost, complexities of design and test, and etc. This paper describes two important and detail challenges: High power consumption and rampant process variations (PV) in nanometer regime. This paper includes following three parts. First, it consecutively describes components of IC power consumption, several negative influences originated from high power, and mainstream low-power design methods. Second, it consecutively describes components of process variations, their negative influences on IC design, and statistical algorithm that studies about static delay analysis (STA), power analysis, and low-power design. Last, combining with the authors’ own research, this paper simply presents hot research topics on these two challenges of next-generation IC design. keywords Integrated Circuit(IC); nanometer technology; power consumption; performance; low-power design; process variation background With scaling IC into nanometer regime, high power consumption becomes the earmark of high-end chips such as CPU and GPU owing to high work frequency and high integrations, which in turn erodes the chip performance. Thus low-power design methodology is needed to reduce power for guaranteeing the performance and each year thousands of papers are published on this topic. In general, low-power design methodology includes the sub-topics: static timing analysis (STA), power analysis (PA), and low-power optimization (LPO). Another by-product of nanometer technology is rampant process variations (PV) that impacts visible influences on STA, PA, and LPO. In recent years, nearly half of papers published on DAC and ICCAD are on how to estimate and manage PV influences which consists of the main part of DFM (Design for Manufacturing). Based on what he has done on low-power design, the author writes this article to let his compatriot scholars to care these two problems and do more academic research on these topics.